NPU-E2E
An educational full-stack NPU accelerator demo featuring a 16×16 systolic array RTL design, AXI4 SoC integration, C/Python runtime, UART driver, and TVM BYOC compiler backend, verified on FPGA with LeNet-5 inference.
It fills a gap in open-source GPU education by providing a simple, documented design with simulation and actual silicon fabrication support via TinyTapeout, along with both open-source and commercial ASIC flows.
A minimal GPU implementation in Verilog optimized for learning about how GPUs work from the ground up.
Built with [!IMPORTANT]
tiny-gpu is a minimal GPU implementation optimized for learning about how GPUs work from the ground up.
Specifically, with the trend toward general-purpose GPUs (GPGPUs) and ML-accelerators like Google's TPU, tiny-gpu focuses on highlighting the general principles of all of these architectures, rather than on the details of graphics-specific hardware.
With this motivation in mind, we can simplify GPUs by cutting out the majority of complexity involved with building a production-grade graphics card, and focus on the core elements that are critical to all of these modern hardware accelerators.
This project is primarily focused on exploring:
After understanding the fundamentals laid out in this project, you can checkout the advanced functionality section to understand some of the most important optimizations made in production grade GPUs (that are more challenging to implement) which improve performance.
tiny-gpu is built to execute a single kernel at a time.
In order to launch a kernel, we need to do the following:
The GPU itself consists of the following units:
The device control register usually stores metadata specifying how kernels should be executed on the GPU.
In this case, the device control register just stores the thread_count - the total number of threads to launch for the active kernel.
Once a kernel is launched, the dispatcher is the unit that actually manages the distribution of threads to different compute cores.
The dispatcher organizes threads
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