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NPU-E2E
An educational full-stack NPU accelerator demo featuring a 16×16 systolic array RTL design, AXI4 SoC integration, C/Python runtime, UART driver, and TVM BYOC compiler backend, verified on FPGA with LeNet-5 inference.
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License
AGPL-3.0
Last updated
2026-07-29
AI repository intelligence
FR-AI / ANALYSISWhy it is worth attention
It provides a complete, end-to-end open-source NPU design from RTL to neural network inference, including hardware verification on real silicon and integration with the TVM compiler stack, making it a rare educational resource.
Who it is for
- Hardware engineers learning systolic array and SoC design
- ML compiler developers exploring TVM BYOC backends
- Students and researchers in computer architecture and accelerators
- FPGA enthusiasts building custom neural network accelerators
Use cases
- Teaching NPU architecture and full-stack accelerator design
- Prototyping and researching systolic array and dataflow strategies
- Developing and testing custom TVM codegen targets for NPUs
- Running small neural networks like LeNet-5 on low-power embedded hardware
Strengths
- Complete pipeline from RTL to inference with TVM BYOC integration
- Hardware-verified on a Xilinx FPGA at 175 MHz achieving 44.8 GMAC/s
- 17 self-checking testbenches and golden model ensure correctness
- Comprehensive documentation including module specs and architectural principles in both English and Chinese
Considerations
- Supports only INT8 precision, not floating-point or mixed-precision
- Designed specifically for the Xilinx XCZU4EV board; porting to other FPGAs requires adaption
- UART transport is extremely slow (~1 s per image), limiting practical deployment without PCIe/Ethernet
- Licensed under AGPLv3, which may restrict commercial or closed-source use
README quick start
Quick Start
Description
End-to-End NPU: RTL systolic array → AXI4 SoC → TVM compiler → FPGA inference
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