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FR-AI / ANALYSISWhy it is worth attention
It achieves high accuracy through decap-informed synchronous models of the custom sprite doorway and CF37201 chip, a cycle-sensitive WAIT handshake, and a Verilator-based verification pipeline that regresses against MAME captures across all nine games.
Who it is for
- MiSTer FPGA owners seeking accurate arcade cores
- Arcade preservationists and hardware reverse engineers
- FPGA developers studying arcade hardware emulation
- Retro gaming enthusiasts wanting a single-core solution for multiple games
Use cases
- Playing the nine supported arcade titles on a MiSTer setup with accurate timing and video output
- Validating hardware accuracy by running the automated regression suite against MAME captures
- Experimenting with PCB audio stage and experimental framebuffer render options
- Learning about cycle-stealing Z80 synchronization and CF37201 register modeling
Strengths
- Cycle-accurate modeling of three Z80s, TMS1025 input, four SN76489A PSGs, and HD6845 raster interrupts
- Runtime game selection via a single RBF and per-game MRA files, reducing FPGA rebuilds
- Comprehensive verification with Verilator, MAME timing runs, and a 361-frame Do! Run Run check
- Open source with detailed documentation, Quartus build results, and a PowerShell-based validation pipeline
Considerations
- Experimental features (e.g., CF framebuffer, CURSOR IRQ) are not fully accurate and may have missing sprites
- ROMs are not distributed; users must supply their own dumps alongside the source
- Requires Quartus 17.0.2 or compatible toolchain and familiarity with FPGA builds
README quick start
Universal Do! Castle Hardware for MiSTer
One runtime-selectable FPGA core for the Universal Do's Castle board family. The release target is Universal_DoCastle.rbf, selected by a separate MRA for each game.
Supported sets
| ID | MAME set | Game | Profile | Rotation |
|---|---|---|---|---|
| 00 | docastle | Mr. Do's Castle | Castle | ROT270 |
| 01 | douni | Mr. Do! vs. Unicorns | Castle | ROT270 |
| 02 | dorunrun | Do! Run Run | Run Run | ROT0 |
| 03 | dowild | Mr. Do's Wild Ride | Run Run | ROT0 |
| 04 | jjack | Jumping Jack | Run Run | ROT270 |
| 05 | kickridr | Kick Rider | Run Run | ROT0 |
| 06 | spiero | Super Pierrot | Run Run | ROT0 |
| 07 | idsoccer | Indoor Soccer | Soccer | ROT0 |
| 08 | asoccer | American Soccer | Soccer | ROT0 |
The core models three 4 MHz Z80s, the cycle-sensitive main/sub WAIT handshake, TMS1025 input pipeline, four SN76489A PSGs with READY-driven wait, live board-relevant HD6845 registers and raster outputs, profile-specific CPU maps and tile priority, standard and Soccer sprite formats, Soccer dual-stick inputs, and Soccer MSM5205 ADPCM through a pinned JT5205 implementation. It also includes the main-board watchdog and a decap-informed synchronous model of the third-CPU/CF37201 sprite doorway. The wrapper provides OSD-controlled CRT H-Size, H-Position, and V-Shift through the pinned MiSTer-CRT-Adjust core-side implementation, plus selectable normal or full H+V integer HDMI scaling.
PCB support options
The default remains the nine-game visually proven path. PCB support enables
the dumped third CPU's two real transfer phases, the decoded CF37201 registers,
the chip's 126-MCLK /PL/interrupt cycle, and the three-second watchdog while
retaining the proven renderer. The CF model now uses the decap-derived address,
counter, flip, palette, and field-select equations. This mode completed
software regressions for all nine sets and a 361-frame Do! Run Run timing run.
PCB audio stage adds a 48 kHz approximation of the service-manual output
coupling and speaker roll-off. Experimental CF framebuffer selects the full
two-field 64K renderer driven only by the real third-CPU/CF stream; it remains
opt-in because the central title sprite is still missing in comparison with
the proven renderer. Experimental IRQ compares the schematic CURSOR source
with validated VSYNC behavior. CURSOR mode is not a release default: t
Description
MiSTer FPGA core for Universal Do! Castle arcade hardware
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