jberdkan
tiny-gpu
Tiny-GPU is a minimal, open-source GPU implementation in Verilog designed for learning how GPUs work from the ground up, with working kernels, full documentation, and ASIC tapeout flows.
Agentic4SystemSummerSchoolContest
A 2026 summer school GPGPU agent acceleration design competition with three independent tracks covering EDA tools, GPGPU RTL design, and compiler/runtime/operator scheduling based on a custom AEC ISA.
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MIT
Last updated
2026-07-28
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FR-AI / ANALYSISWhy it is worth attention
This is a full-stack chip design competition that spans from EDA software to hardware RTL to compiler/software stack, with detailed scoring, public test cases, and strict academic integrity rules, making it a comprehensive benchmark for talent in chip design and AI acceleration.
Who it is for
- Undergraduate and graduate students in EE/CS
- Chip design enthusiasts interested in GPGPU
- Researchers and developers in AI accelerators
- Open-source EDA and compiler toolchain developers
Use cases
- Educational competition for hands-on chip design learning
- Validation of custom ISA-based GPGPU architectures
- Benchmarking EDA tools (simulation, verification, synthesis) on real designs
- Training and inference model deployment on custom GPGPU
Strengths
- Three independent tracks covering end-to-end design: EDA, RTL, and software stack
- Well-defined scoring normalization and public test cases for objective comparison
- Support for LLM-assisted development with required disclosure
- Clear competition rules and anti-cheating measures ensure fairness
Considerations
- Requires strong background in both hardware and software, limiting accessibility
- Relies on specific tool versions (Verilator, Yosys, OpenSTA) and PDK (Nangate45, ASAP7)
- No network access during evaluation, all dependencies must be pre-packaged
README quick start
Agentic4Systems暑期学校GPGPU智能体加速设计竞赛 2026
面向本科生与研究生的综合性芯片设计竞赛 基于自定义 AEC (Array Execution Core) ISA，完成 GPGPU RTL 设计、EDA 工具链与软件栈开发
2026 年度 · 三赛道独立评分
竞赛简介
本竞赛围绕一个完整的 GPGPU 芯片全栈设计，设置三个平行赛道，参赛队伍选择其一完成。三个赛道覆盖：
- 赛道 A：自研 EDA 工具（仿真、验证、综合）
- 赛道 B：AEC GPGPU RTL 设计（基于自研 128-bit 定长 ISA）
- 赛道 C：编译器、Runtime 与算子调度
每个赛道独立评分、独立评审。
+--------------------------------------------------------------+
| AEC GPGPU 竞赛全栈结构 |
+--------------------------------------------------------------+
| |
| +------------------------------------------------------+ |
| | 赛道 A：EDA 软件 | |
| | | |
| | A1 轻量 RTL 仿真器 --+ | |
| | A2 验证环境自动生成 --+ 为赛道 B | |
| | A3 轻量 RTL 逻辑综合工具 --+ 提供工具链 | |
| +------------------------------------------------------+ |
| | |
| v |
| +------------------------------------------------------+ |
| | 赛道 B：GPGPU RTL 设计 | |
| | | |
| | 基于 AEC 128-bit 定长 ISA | |
| | RTL + CModel + 构建脚本 + 报告 | |
| | | |
| | 为赛道 C 提供：精确 C 模型 (Golden Model) | |
| +------------------------------------------------------+ |
| | |
| v |
| +------------------------------------------------------+ |
| | 赛道 C：编译器 & Runtime & 算子调度 | |
| | | |
| | C1 AEC IR 编译器 (PTX 风格 -> AEC ISA) | |
| | C2 主机侧驱动 (libaec.so + 虚拟设备) | |
| | C3 算子调度 (ONNX -> AEC GPGPU 推理) | |
| +------------------------------------------------------+ |
| |
+--------------------------------------------------------------+
竞赛规则与学术诚信
原创性要求
本竞赛要求所有参赛作品为**队伍
Description
Contests
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