YutongChenVictor
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NPU-E2E
An educational full-stack NPU accelerator demo featuring a 16×16 systolic array RTL design, AXI4 SoC integration, C/Python runtime, UART driver, and TVM BYOC compiler backend, verified on FPGA with LeNet-5 inference.
AI 仓库情报摘要
FR-AI / ANALYSIS为什么值得关注
它填补了开源 GPU 教育的空白，提供了一个简单、有文档的设计，支持仿真和通过 TinyTapeout 实际制造，同时包含开源和商业 ASIC 流程。
适合谁使用
- 希望了解 GPU 内部原理的硬件学习者
- Verilog 和 ASIC 设计学生
- 开源硬件爱好者和 TinyTapeout 用户
- 教授计算机体系结构或 GPU 设计的教师
典型使用场景
- 学习 GPU 架构、指令集和并行执行
- 仿真并追踪矩阵加法和乘法内核的执行
- 使用开源或商业工具实践从 RTL 到 GDS 的 ASIC 实现
- 通过提供的适配在 TinyTapeout 上制造功能性 GPU
项目优势
- 完整、文档完善的 15 个 Verilog 文件设计
- 可运行的内核（矩阵加法和乘法），支持执行轨迹和仿真
- 多种 ASIC 实现流程：开源 (LibreLane on sky130) 和商业 (Cadence on OSU05)
- TinyTapeout 适配器包含片上内存、主机驱动和可流片的交付件
使用前须知
- 架构简化：不支持分支发散、流水线、线程束调度或内存合并
- 需要外部工具（Icarus、Cocotb、sv2v）进行仿真，非即插即用
- 流片限于特定工艺（sky130、OSU05），并受 TinyTapeout 引脚限制
README 快速开始
tiny-gpu
A minimal GPU implementation in Verilog optimized for learning about how GPUs work from the ground up.
Built with [!IMPORTANT]
tiny-gpu is a minimal GPU implementation optimized for learning about how GPUs work from the ground up.
Specifically, with the trend toward general-purpose GPUs (GPGPUs) and ML-accelerators like Google's TPU, tiny-gpu focuses on highlighting the general principles of all of these architectures, rather than on the details of graphics-specific hardware.
With this motivation in mind, we can simplify GPUs by cutting out the majority of complexity involved with building a production-grade graphics card, and focus on the core elements that are critical to all of these modern hardware accelerators.
This project is primarily focused on exploring:
- Architecture - What does the architecture of a GPU look like? What are the most important elements?
- Parallelization - How is the SIMD progamming model implemented in hardware?
- Memory - How does a GPU work around the constraints of limited memory bandwidth?
After understanding the fundamentals laid out in this project, you can checkout the advanced functionality section to understand some of the most important optimizations made in production grade GPUs (that are more challenging to implement) which improve performance.
Architecture
GPU
tiny-gpu is built to execute a single kernel at a time.
In order to launch a kernel, we need to do the following:
- Load global program memory with the kernel code
- Load data memory with the necessary data
- Specify the number of threads to launch in the device control register
- Launch the kernel by setting the start signal to high.
The GPU itself consists of the following units:
- Device control register
- Dispatcher
- Variable number of compute cores
- Memory controllers for data memory & program memory
- Cache
Device Control Register
The device control register usually stores metadata specifying how kernels should be executed on the GPU.
In this case, the device control register just stores the thread_count - the total number of threads to launch for the active kernel.
Dispatcher
Once a kernel is launched, the dispatcher is the unit that actually manages the distribution of threads to different compute cores.
The dispatcher organizes threads
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