为什么值得关注

通过基于芯片解剖的同步模型（包括自定义精灵门控和 CF37201 芯片）、周期敏感的 WAIT 握手以及基于 Verilator 的验证流水线（对所有九款游戏进行 MAME 捕捉回归）实现了高精度。

适合谁使用

寻求精确街机核心的 MiSTer FPGA 用户
从事街机保存和硬件逆向工程的爱好者
研究街机硬件模拟的 FPGA 开发者
希望单核心运行多款游戏的复古游戏发烧友

典型使用场景

在 MiSTer 设备上游玩九款支持的街机游戏，享受精确的时序和视频输出
通过自动化回归套件与 MAME 捕捉对比来验证硬件精度
实验 PCB 音频级和实验性帧缓冲渲染选项
学习周期窃取 Z80 同步和 CF37201 寄存器建模

项目优势

周期精确模拟三个 Z80、TMS1025 输入、四个 SN76489A 声道及 HD6845 光栅中断
通过单一 RBF 和每个游戏的 MRA 文件实现运行时游戏选择，减少 FPGA 重建次数
综合验证：Verilator、MAME 时序运行及 361 帧的 Do! Run Run 检查
开源，提供详细文档、Quartus 构建结果和基于 PowerShell 的验证流水线

使用前须知

实验性功能（如 CF 帧缓冲、CURSOR IRQ）尚未完全精确，可能存在缺失精灵
ROM 不随源码分发，用户需自行提供
需要 Quartus 17.0.2 或兼容工具链，并具备 FPGA 构建经验

README 快速开始

Universal Do! Castle Hardware for MiSTer

One runtime-selectable FPGA core for the Universal Do's Castle board family. The release target is Universal_DoCastle.rbf, selected by a separate MRA for each game.

Supported sets

ID	MAME set	Game	Profile	Rotation
00	docastle	Mr. Do's Castle	Castle	ROT270
01	douni	Mr. Do! vs. Unicorns	Castle	ROT270
02	dorunrun	Do! Run Run	Run Run	ROT0
03	dowild	Mr. Do's Wild Ride	Run Run	ROT0
04	jjack	Jumping Jack	Run Run	ROT270
05	kickridr	Kick Rider	Run Run	ROT0
06	spiero	Super Pierrot	Run Run	ROT0
07	idsoccer	Indoor Soccer	Soccer	ROT0
08	asoccer	American Soccer	Soccer	ROT0

The core models three 4 MHz Z80s, the cycle-sensitive main/sub WAIT handshake, TMS1025 input pipeline, four SN76489A PSGs with READY-driven wait, live board-relevant HD6845 registers and raster outputs, profile-specific CPU maps and tile priority, standard and Soccer sprite formats, Soccer dual-stick inputs, and Soccer MSM5205 ADPCM through a pinned JT5205 implementation. It also includes the main-board watchdog and a decap-informed synchronous model of the third-CPU/CF37201 sprite doorway. The wrapper provides OSD-controlled CRT H-Size, H-Position, and V-Shift through the pinned MiSTer-CRT-Adjust core-side implementation, plus selectable normal or full H+V integer HDMI scaling.

PCB support options

The default remains the nine-game visually proven path. PCB support enables the dumped third CPU's two real transfer phases, the decoded CF37201 registers, the chip's 126-MCLK /PL/interrupt cycle, and the three-second watchdog while retaining the proven renderer. The CF model now uses the decap-derived address, counter, flip, palette, and field-select equations. This mode completed software regressions for all nine sets and a 361-frame Do! Run Run timing run.

PCB audio stage adds a 48 kHz approximation of the service-manual output coupling and speaker roll-off. Experimental CF framebuffer selects the full two-field 64K renderer driven only by the real third-CPU/CF stream; it remains opt-in because the central title sprite is still missing in comparison with the proven renderer. Experimental IRQ compares the schematic CURSOR source with validated VSYNC behavior. CURSOR mode is not a release default: t

项目描述

MiSTer FPGA core for Universal Do! Castle arcade hardware

mrdo