fatemekhasraji
FashionMnist_LeNet5
An open-source SystemVerilog implementation of a LeNet-5 CNN accelerator for Fashion-MNIST inference, built around a 5×5 2D torus systolic array with Q8.8 fixed-point arithmetic.
AI 仓库情报摘要
FR-AI / ANALYSIS为什么值得关注
该仓库提供了可检查的、商用级别的 FPGA 硬件 TCP/IP 卸载引擎，包含详细的连接查找、状态管理和重传 RTL，是高性能网络设计的宝贵参考。
适合谁使用
- 从事自定义网络栈的 FPGA 与 RTL 设计师
- 研究硬件 TCP/IP 卸载与传输协议的学者
- 开发低延迟或确定性以太网应用的工程师
- 对高级 FPGA 数字设计感兴趣的学生或爱好者
典型使用场景
- 构建基于 FPGA 的硬件 TCP 终止网络接口
- 原型设计低延迟交易或工业控制系统
- 教学探索硬件中的 TCP 状态机与 ARP 逻辑
- 评估自定义以太网加速的卸载架构权衡
项目优势
- 完整实现了 TCP 连接建立、确认和重传超时的硬件逻辑
- 高效的四种方式哈希连接元组缓存，支持 Toeplitz 替代哈希
- 公开真实设计的 RTL 快照，附带详细文档
- 集成了带学习、请求/回复和过期条目老化功能的 ARP 子系统
使用前须知
- TCP 功能不完整：缺少拥塞控制、接收窗口、TCP 选项和乱序缓存
- 不支持独立构建：依赖排除的发送有效负载存储和 Xilinx IP 核
- 许可证受限：仅源码可用，对商业使用和再分发有限制
README 快速开始
RTL-NIC v0
RTL-NIC v0 is a custom SystemVerilog RTL architecture for FPGA Ethernet receive and transmit datapaths with ARP, IPv4, UDP, and specialized TCP handling. The design includes four-way connection-tuple lookup, 64 TCP control block entries, centralized state writeback, connection establishment and state transitions, retransmission-timeout scheduling, transmit-frame construction, and a 1 Gb/s Xilinx PCS/PMA integration.
This repository is a source-available architectural snapshot derived from the broader private TradingNIC implementation. It preserves an inspectable version of the design under a custom license; it is not presented as open source.
Demo video: Watch the project demonstration on LinkedIn
The receive path carries byte-wide GMII traffic from the PCS/PMA into
rx_datapath, which detects the preamble/SFD and decodes Ethernet, ARP, IPv4,
TCP, and UDP fields. ARP traffic is routed to the ARP subsystem, while matching
IPv4/TCP traffic and the fixed-format UDP application interface feed the TCP
control path.
The transmit path accepts ARP and TCP descriptors, constructs Ethernet frames with IPv4 and TCP checksums where applicable, queues each frame, and serializes the preamble, padded frame body, FCS, and inter-frame gap onto GMII.
Technical Highlights
- A four-way connection-tuple cache maps IPv4 source/destination addresses and TCP source/destination ports to TCB addresses.
- Two matrix-based Toeplitz hash results provide alternative lookup and placement locations for the connection cache.
- A 64-entry true dual-port TCB store holds per-connection transport state.
- Received TCP traffic and application requests share the tuple-cache lookup pipeline through a common arbiter.
tcb_mgrcoordinates the control paths and commits their updates through a centralized state-writeback path.- Active connection requests can wait in an eight-entry pending table while ARP resolves the destination MAC address.
tcp_ctrlandtcp_fsmimplement specialized connection establishment, acknowledgment processing, response generation, and connection-state transitions.- The RTO path combines timer-wheel scheduling, cancellation, immediate priority work, and increasing retry-backoff state.
- The ARP subsystem provides a four-way, 16-set cache with pa
项目描述
Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.
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