MoonshotAI
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Kimi-K3
Kimi K3 is an open-weight, 2.8T-parameter native multimodal agentic model with a 1M-token context window, designed for frontier coding, knowledge work, and reasoning tasks.
AI 仓库情报摘要
FR-AI / ANALYSIS为什么值得关注
该项目展示了从PyTorch训练、量化到位精确仿真和Artix-7 FPGA综合的完整硬件设计流程，在仅使用FP32一半存储空间的前提下达到90.1%准确率，推理延迟低于1毫秒。
适合谁使用
- FPGA与硬件加速器设计人员
- 研究CNN脉动阵列拓扑的学者
- 学习机器学习数字设计的学生或工程师
- 面向低功耗边缘推理的嵌入式系统开发者
典型使用场景
- 在资源受限的FPGA上实时进行Fashion-MNIST分类
- 在神经加速器中对比定点与浮点精度的基准测试
- 作为使用环形脉动阵列实现CNN层（卷积、池化、全连接）的教学参考
- 扩展设计至更大数据集或更深网络的起点
项目优势
- 创新的二维环形拓扑消除了全局广播，减少了布线拥塞并提升了时钟频率（Artix-7上f_max达127 MHz）。
- 详尽的量化研究表明Q8.8定点相比FP32减少50%存储，精度损失小于1.1%。
- 在小尺寸Artix-7上资源利用率极低（LUT 2.55%、寄存器2.53%、DSP 10.42%），为额外逻辑留出充足空间。
- 完整的开源流程，包括位精确Python模拟器、RTL测试台及Vivado项目，便于复现。
使用前须知
- 仅针对特定LeNet-5架构和Fashion-MNIST数据集设计，非通用CNN加速器。
- 综合结果基于单一Artix-7器件，在其他FPGA上性能和资源使用可能不同。
- 自述文件中未提供功耗或能效测量数据。
README 快速开始
FPGA Acceleration of LeNet-5 CNN for Fashion-MNIST via 2D Torus Systolic Array
-green)
📌 Project Overview
This repository contains a full SystemVerilog hardware accelerator for the LeNet-5 Convolutional Neural Network (CNN), optimized for inference on the Fashion-MNIST dataset.
At the core of the datapath is a customized 5x5 2D Torus Systolic Array that accelerates General Matrix Multiplication (GEMM) using im2col lowering for 5x5 Convolutional layers, Fully Connected (FC) layers, and inline 2x2 Average Pooling.
The repository features a complete end-to-end flow:
- PyTorch Model Training & Weight Quantization (Floating-point to Q8.8 Fixed-Point conversion).
- Bit-Exact Software Simulator (
full_fixed_sim.py) for golden reference verification. - RTL Design & Testbench in SystemVerilog, validated through Vivado XSim.
🏗 System Architecture
1. LeNet-5 Top-Level Hardware Pipeline (Top.sv)
graph LR
IMG["Input Image(32×32 Q8.8)"] --> C1["Conv1(6 @ 28×28)"]
C1 --> P1["Pool1(6 @ 14×14)"]
P1 --> C2["Conv2(16 @ 10×10)"]
C2 --> P2["Pool2(16 @ 5×5)"]
P2 --> C3["Conv3(120 @ 1×1)"]
C3 --> FC1["FC1(84 Neurons)"]
FC1 --> FC2["FC2(10 Neurons)"]
FC2 --> ARG["ArgmaxPredicted Class (0-9)"]
style IMG fill:#1e293b,stroke:#38bdf8,color:#fff
style C1 fill:#1e293b,stroke:#34d399,color:#fff
style P1 fill:#1e293b,stroke:#f59e0b,color:#fff
style C2 fill:#1e293b,stroke:#34d399,color:#fff
style P2 fill:#1e293b,stroke:#f59e0b,color:#fff
style C3 fill:#1e293b,stroke:#34d399,color:#fff
style FC1 fill:#1e293b,stroke:#c084fc,color:#fff
style FC2 fill:#1e293b,stroke:#c084fc,color:#fff
style ARG fill:#1e293b,stroke:#34d399,color:#fff
2. Torus Systolic Array Mapping
1. 2D Torus Systolic Array (SA.sv)
- Structure: 5x5 Processing Element (PE) matrix connected in a 2D toroidal topology.
- Toroidal Wrapping: Left-shift and Up-shift outputs wrap cyclically around array edges.
- Benefits: Eliminates global data broadcast signals, reduces routing congestion, and increases clock frequency compared to standard global broadcast architectures.
2. Processing Element (PE.sv)
- MAC Engine: 16-bit signed fixed-point multiplier with 32-bit accumulator.
- Fixed-Point Specification: Q8.8 format (8 integer bits, 8 fractional bit
项目描述
SystemVerilog FPGA acceleration of LeNet-5 CNN for Fashion-MNIST classification, powered by a 5x5 2D Torus Systolic Array with bit-exact Python simulator, and out-of-context Vivado synthesis benchmarks.
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