Why it is worth attention

It provides an inspectable, commercial-grade hardware TCP/IP offload engine designed for FPGAs, with detailed RTL for connection lookup, state management, and retransmission, offering valuable reference for high-performance networking designs.

Who it is for

FPGA and RTL designers working on custom networking stacks
Researchers studying hardware TCP/IP offload and transport protocols
Engineers developing low-latency or deterministic Ethernet applications
Students or hobbyists interested in advanced FPGA digital design

Use cases

Building FPGA-based network interfaces with hardware TCP termination
Prototyping low-latency trading or industrial control systems
Educational exploration of TCP state machine and ARP logic in hardware
Evaluating offload architecture trade-offs for custom Ethernet acceleration

Strengths

Full hardware implementation of TCP connection establishment, acknowledgment, and retransmission timeout
Efficient four-way hashed connection-tuple cache with Toeplitz hash alternatives
Publicly available RTL snapshot of a real-world design with detailed documentation
Integrated ARP subsystem with learning, request/reply, and stale-entry aging

Considerations

Incomplete TCP feature set: no congestion control, receive window enforcement, TCP options, or out-of-order buffering
Standalone build not supported: depends on excluded transmit-payload memory and Xilinx IP cores
Limited license: source-available with restrictions on commercial use and redistribution

README quick start

RTL-NIC v0

RTL-NIC v0 is a custom SystemVerilog RTL architecture for FPGA Ethernet receive and transmit datapaths with ARP, IPv4, UDP, and specialized TCP handling. The design includes four-way connection-tuple lookup, 64 TCP control block entries, centralized state writeback, connection establishment and state transitions, retransmission-timeout scheduling, transmit-frame construction, and a 1 Gb/s Xilinx PCS/PMA integration.

This repository is a source-available architectural snapshot derived from the broader private TradingNIC implementation. It preserves an inspectable version of the design under a custom license; it is not presented as open source.

Demo video: Watch the project demonstration on LinkedIn

The receive path carries byte-wide GMII traffic from the PCS/PMA into rx_datapath, which detects the preamble/SFD and decodes Ethernet, ARP, IPv4, TCP, and UDP fields. ARP traffic is routed to the ARP subsystem, while matching IPv4/TCP traffic and the fixed-format UDP application interface feed the TCP control path.

The transmit path accepts ARP and TCP descriptors, constructs Ethernet frames with IPv4 and TCP checksums where applicable, queues each frame, and serializes the preamble, padded frame body, FCS, and inter-frame gap onto GMII.

Technical Highlights

A four-way connection-tuple cache maps IPv4 source/destination addresses and TCP source/destination ports to TCB addresses.
Two matrix-based Toeplitz hash results provide alternative lookup and placement locations for the connection cache.
A 64-entry true dual-port TCB store holds per-connection transport state.
Received TCP traffic and application requests share the tuple-cache lookup pipeline through a common arbiter.
tcb_mgr coordinates the control paths and commits their updates through a centralized state-writeback path.
Active connection requests can wait in an eight-entry pending table while ARP resolves the destination MAC address.
tcp_ctrl and tcp_fsm implement specialized connection establishment, acknowledgment processing, response generation, and connection-state transitions.
The RTO path combines timer-wheel scheduling, cancellation, immediate priority work, and increasing retry-backoff state.
The ARP subsystem provides a four-way, 16-set cache with pa

Description

Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.

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