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Kimi-K3
Kimi K3 is an open-weight, 2.8T-parameter native multimodal agentic model with a 1M-token context window, designed for frontier coding, knowledge work, and reasoning tasks.
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FR-AI / ANALYSISWhy it is worth attention
It demonstrates a complete, end-to-end hardware design flow—from PyTorch training and quantization to bit-exact simulation and RTL synthesis on an Artix-7 FPGA—achieving 90.1% accuracy with only 50% memory footprint of FP32 and sub-millisecond latency.
Who it is for
- FPGA and hardware accelerator designers
- Researchers exploring systolic array topologies for CNNs
- Students or engineers learning digital design for machine learning
- Embedded system developers targeting low-power edge inference
Use cases
- Real-time Fashion-MNIST classification on resource-constrained FPGAs
- Benchmarking fixed-point vs. floating-point accuracy trade-offs in neural accelerators
- Educational reference for implementing CNN layers (conv, pool, FC) with a toroidal systolic array
- Starting point for extending the design to larger datasets or deeper networks
Strengths
- Innovative 2D torus topology eliminates global broadcasts, reducing routing congestion and enabling higher clock frequencies (f_max 127 MHz on Artix-7).
- Rigorous quantization study shows Q8.8 fixed-point cuts memory by 50% with <1.1% accuracy loss compared to FP32.
- Very low resource utilization (2.55% LUTs, 2.53% registers, 10.42% DSPs) on a small Artix-7, leaving ample room for additional logic.
- Complete open-source flow with bit-exact Python simulator, RTL testbench, and Vivado project ready for reproduction.
Considerations
- Designed only for the specific LeNet-5 architecture and Fashion-MNIST dataset; not a general-purpose CNN accelerator.
- Synthesis results based on a single Artix-7 device; performance and resource usage may vary on other FPGAs.
- No power consumption or energy efficiency measurements provided in the README.
README quick start
FPGA Acceleration of LeNet-5 CNN for Fashion-MNIST via 2D Torus Systolic Array
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📌 Project Overview
This repository contains a full SystemVerilog hardware accelerator for the LeNet-5 Convolutional Neural Network (CNN), optimized for inference on the Fashion-MNIST dataset.
At the core of the datapath is a customized 5x5 2D Torus Systolic Array that accelerates General Matrix Multiplication (GEMM) using im2col lowering for 5x5 Convolutional layers, Fully Connected (FC) layers, and inline 2x2 Average Pooling.
The repository features a complete end-to-end flow:
- PyTorch Model Training & Weight Quantization (Floating-point to Q8.8 Fixed-Point conversion).
- Bit-Exact Software Simulator (
full_fixed_sim.py) for golden reference verification. - RTL Design & Testbench in SystemVerilog, validated through Vivado XSim.
🏗 System Architecture
1. LeNet-5 Top-Level Hardware Pipeline (Top.sv)
graph LR
IMG["Input Image(32×32 Q8.8)"] --> C1["Conv1(6 @ 28×28)"]
C1 --> P1["Pool1(6 @ 14×14)"]
P1 --> C2["Conv2(16 @ 10×10)"]
C2 --> P2["Pool2(16 @ 5×5)"]
P2 --> C3["Conv3(120 @ 1×1)"]
C3 --> FC1["FC1(84 Neurons)"]
FC1 --> FC2["FC2(10 Neurons)"]
FC2 --> ARG["ArgmaxPredicted Class (0-9)"]
style IMG fill:#1e293b,stroke:#38bdf8,color:#fff
style C1 fill:#1e293b,stroke:#34d399,color:#fff
style P1 fill:#1e293b,stroke:#f59e0b,color:#fff
style C2 fill:#1e293b,stroke:#34d399,color:#fff
style P2 fill:#1e293b,stroke:#f59e0b,color:#fff
style C3 fill:#1e293b,stroke:#34d399,color:#fff
style FC1 fill:#1e293b,stroke:#c084fc,color:#fff
style FC2 fill:#1e293b,stroke:#c084fc,color:#fff
style ARG fill:#1e293b,stroke:#34d399,color:#fff
2. Torus Systolic Array Mapping
1. 2D Torus Systolic Array (SA.sv)
- Structure: 5x5 Processing Element (PE) matrix connected in a 2D toroidal topology.
- Toroidal Wrapping: Left-shift and Up-shift outputs wrap cyclically around array edges.
- Benefits: Eliminates global data broadcast signals, reduces routing congestion, and increases clock frequency compared to standard global broadcast architectures.
2. Processing Element (PE.sv)
- MAC Engine: 16-bit signed fixed-point multiplier with 32-bit accumulator.
- Fixed-Point Specification: Q8.8 format (8 integer bits, 8 fractional bit
Description
SystemVerilog FPGA acceleration of LeNet-5 CNN for Fashion-MNIST classification, powered by a 5x5 2D Torus Systolic Array with bit-exact Python simulator, and out-of-context Vivado synthesis benchmarks.
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