NPU-E2E
An educational full-stack NPU accelerator demo featuring a 16×16 systolic array RTL design, AXI4 SoC integration, C/Python runtime, UART driver, and TVM BYOC compiler backend, verified on FPGA with LeNet-5 inference.
它将整个SNN领域在一个地方组织起来,包含“从这里开始”的里程碑工作表格、每项资源的“为什么重要”说明,以及英文和中文两个版本,方便研究者、从业者和学生使用。
Awesome Spiking Neural Networks Hub
A comprehensive, deeply-annotated guide to the world of Spiking Neural Networks (SNNs) papers · models · neuromorphic hardware · datasets · tools · research groups
English · 中文 | Timeline edition
340+ papers & resources · 40+ seminal works · 42 research groups · 45+ open-source projects
Jump to Start Here · Fundamentals · Learning & Models · Hardware · Applications · Topics · Resources · Groups
If this guide helps your work, please star the repo and cite it — contributions are very welcome.
Conventional deep networks (ANNs) pass continuous numbers between neurons at every layer, synchronously, every forward pass. A Spiking Neural Network instead communicates with discrete, binary events — "spikes" — in time, exactly like biological neurons. A spiking neuron integrates incoming current onto a membrane potential; when that potential crosses a threshold, it emits a single spike and resets. Nothing happens when there is no spike.
Three consequences make SNNs compelling:
The central difficulty is that a spike is a step function — non-differentiable — so ordinary backpropagation does not directly apply. The whole field, in a sense, is a set of answers to "how do we train these things?" — which is why the Training Methods section is the heart of this list.
This is an awesome-style hub for the whole SNN field — papers, models, hardware, datasets, tools, and research groups. Each entry carries a one-line "why it matters" note (English here; 中文 in the Chinese edition) so you can navigate without drowning.
12 must-read landmarks that trace the field's arc — f
The comprehensive bilingual (EN/中文) hub for Spiking Neural Networks — 340+ papers, models, neuromorphic hardware, datasets, tools & research groups.
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An educational full-stack NPU accelerator demo featuring a 16×16 systolic array RTL design, AXI4 SoC integration, C/Python runtime, UART driver, and TVM BYOC compiler backend, verified on FPGA with LeNet-5 inference.
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A 28.9 million parameter language model runs on an $8 ESP32-S3 microcontroller entirely on-device, generating simple stories at about 9.5 tokens per second.