It documents the first publicly available method to unlock the full 31 TFLOPS AI compute of the Strix Halo NPU using a mix of open-source (IRON, Peano) and proprietary (Chess, FastFlowLM) components, with verified benchmark results.
Step-by-step guide to unlock the NPU on AMD Ryzen AI Max+ 395 (Strix Halo) — from zero to 31 TFLOPS AI compute.
| Component | Spec |
|---|---|
| CPU | AMD RYZEN AI MAX+ 395 (16 Zen5 cores) |
| GPU | Radeon 8060S (40 RDNA 3.5 CUs) |
| NPU | RyzenAI-npu5 (32 AIE2P tiles) |
| RAM | 128 GB LPDDR5x (unified — CPU/GPU/NPU share) |
| OS | Ubuntu 26.04 LTS |
| Kernel | 7.0.0+ (in-tree amdxdna driver) |
| Benchmark | Result |
|---|---|
| 32-core BFP16 GEMM peak | 31.2 TFLOPS |
| 32-core BFP16 GEMM sustained | 30.9 TFLOPS |
| Gemma 4 2B (FastFlowLM) | 25 tok/s |
| Llama 3.1 8B (FastFlowLM) | 15 tok/s |
# NPU should show as RyzenAI-npu5
sudo xrt-smi examine
Expected output:
[0000:c6:00.1] |RyzenAI-npu5 |
If not present, check the driver is loaded:
lsmod | grep amdxdna
sudo modprobe amdxdna
sudo add-apt-repository ppa:amd-team/xrt
sudo apt update
sudo apt install libxrt2 libxrt-npu2 libxrt-dev libxrt-utils \
libxrt-utils-npu python3-xrt
sudo usermod -aG render $USER
# log out and back in, or: newgrp render
git clone https://github.com/Xilinx/mlir-aie.git
cd mlir-aie
python3 -m venv .venv
source .venv/bin/activate
pip install numpy ml_dtypes
# Install prebuilt wheel
pip install https://github.com/Xilinx/mlir-aie/releases/download/v1.3.2/mlir_aie-1.3.2-cp314-cp314-manylinux_2_35_x86_64.whl
cd .venv/lib/python3.14/site-packages/mlir_aie/python/aie/iron
# Add In/Out/CompileTime markers
cat >> __init__.py /tmp/pt.cc
extern "C" void pt(int32_t* a, int32_t* c, int32_t n) {
for (int i = 0; i /tmp/example-kernel.elf
npu-ctrl kernels register \
--name vec_add \
--artifact /tmp/example-kernel.elf \
--dtype i32 \
--shape N=64 \
--toolchain peano
npu-ctrl kernels list
npu-ctrl bench run --label python-version --warmup 0 --iters 1 -- python3 --version
npu-ctrl bench list
The MVP stores JSON records for devices, toolchains, kernel artifacts, and benchmark runs. Later phases will add AIE kernel builders, profile collection, and compiler experiment integration.
Step-by-step guide to set up Strix Halo NPU (Ryzen AI Max+ 395) with IRON, Peano, Chess, FastFlowLM — 31 TFLOPS
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